Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

Authors:
Yiran Chen;Hai Li;Jing Li;Cheng-Kok Koh
Affiliations:
Seagate Technology;Seagate Technology;Purdue University;Purdue University
Venue:
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Year:
2007

Citing 4
Cited 2

Digital integrated circuits: a design perspective

Digital integrated circuits: a design perspective
Deterministic Clock Gating for Microprocessor Power Reduction

HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Low Power Adder with Adaptive Supply Voltage

ICCD '03 Proceedings of the 21st International Conference on Computer Design
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

Variable-latency design by function speculation

Proceedings of the Conference on Design, Automation and Test in Europe
A general design methodology for synchronous early-completion-prediction adders in nano-CMOS DSP architectures

VLSI Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, the proposed VL-adder can automatically shift data capturing clock edge to tolerate NBTI-induced delay degradation on critical timing paths. VL-adder operates with a fixed supply voltage and clock period, avoiding the high design and manufacturing costs incurred by existing NBTI-tolerant techniques. Compared to other related lower-power adder designs, VL-adder technique always provides better energy efficiency through the whole chip lifetime with very limited performance degradation (4.6% or less).