Variable-latency adder (VL-adder) designs for low power and NBTI tolerance

Authors:
Yiran Chen;Hai Li;Cheng-Kok Koh;Guangyu Sun;Jing Li;Yuan Xie;Kaushik Roy
Affiliations:
Seagate Technology, Bloomington, MN;Department of Electrical and Computer Engineering, Polytechnic Institute of NYU, Brooklyn, NY;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

In this paper, we proposed a new adder design called variable-latency adder (VL-adder). This technique allows the adder to work at a lower supply voltage than that required by a conventional adder while maintaining the same throughput. The VL-adder design can be further modified to overcome the effects of negative bias temperature instability (NBTI) on circuit delay. By applying VL-adder concept to a 64-bit carry-select adder design, more than 40% energy saving is obtained when a similar throughput is maintained.