An evaluation of asynchronous addition

Authors:
D. J. Kinniment
Affiliations:
-
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1996

Citing 0
Cited 4

Asynchronous Parallel Prefix Computation

IEEE Transactions on Computers
Self-Timed Carry-Lookahead Adders

IEEE Transactions on Computers - Special issue on computer arithmetic
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder

PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A general design methodology for synchronous early-completion-prediction adders in nano-CMOS DSP architectures

VLSI Design

Quantified Score

Hi-index	0.01

Visualization

Abstract

There is considerable interest at present in the design of asynchronous systems based on the use of self-timing components for arithmetic and other operations. Amongst the advantages claimed for asynchronous design are ease of design, high speed, low power, and device speed independence. An often quoted example of the speed improvement possible from self-timed hardware is parallel binary addition, where the carry signals in the worst case must propagate through n stages before the sum can be guaranteed correct. In practice, however, it is not possible to achieve significant speed advantage from the method, and this paper shows that asynchronous adders only give a performance improvement over more conventional hardware in very limited conditions, where the size and regularity of the layout are at a premium.