Performance analysis and optimization of asynchronous circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Performance of iterative computation in self-timed rings
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Coping with Latency in SOC Design
IEEE Micro
ANALYSIS OF ASYNCHRONOUS CONCURRENT SYSTEMS BY TIMED PETRI NETS
ANALYSIS OF ASYNCHRONOUS CONCURRENT SYSTEMS BY TIMED PETRI NETS
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Slack Matching Asynchronous Designs
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Slack Matching Quasi Delay-Insensitive Circuits
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Topology-based optimization of maximal sustainable throughput in a latency-insensitive system
Proceedings of the 44th annual Design Automation Conference
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
IEEE Transactions on Software Engineering
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Performance analysis of latency-insensitive systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Throughput optimization for latency-insensitive system with minimal queue insertion
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Challenges in verifying communication fabrics
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Buffer resizing and buffer insertion are two transformation techniques for the performance optimization of elastic systems. Different approaches for each technique have already been proposed in the literature. Both techniques increase the storage capacity and can potentially contribute to improve the throughput of the system. Each technique offers a different trade-off between area cost and latency. This paper presents a method that combines both techniques to achieve the maximum possible throughput while minimizing the cost of the implementation. The provided method is based on mixed integer linear programming. A set of experiments is designed to show the feasibility of the approach.