A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
The Definition of Standard ML
Coping with Latency in SOC Design
IEEE Micro
Modeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation
Modeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
Dataflow Architectures for GALS
Electronic Notes in Theoretical Computer Science (ENTCS)
A trace-based framework for verifiable GALS composition of IPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
| Hi-index | 14.98 |
With increasing clock frequencies, the signal delay on some interconnects in a System on Chip (SoC) often exceeds the clock period, which necessitates latency insensitive protocols (LIPs). The correctness of a system composed of synchronous blocks communicating via LIPs is established by showing latency equivalence between a completely synchronous composition of the blocks, and the LIP-based composition. Every time a new LIP is conceived, it needs to be debugged and then proven correct. Mathematical theorems to establish correctness, though elegant, are error prone, and tedious to create for every new variant of LIPs. In this work, we present validation frameworks for families of LIPs, both for dynamic validation, useful for early debug cycles, and formal verification for formal proof of correctness. This can be a useful framework in the hands of designers trying to create new LIPs or to optimize existing ones for design convergence.