A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proof, language, and interaction
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Modeling concurrent real-time processes using discrete events
Annals of Software Engineering
Synchronous Observers and the Verification of Reactive Systems
AMAST '93 Proceedings of the Third International Conference on Methodology and Software Technology: Algebraic Methodology and Software Technology
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Model Checking via Reachability Testing for Timed Automata
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Specification and verification of time requirements with CCSL and Esterel
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Formal model construction using HDL simulation semantics
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Systems Engineering with SysML/UML: Modeling, Analysis, Design
Systems Engineering with SysML/UML: Modeling, Analysis, Design
Testing Conformance of Real-Time Applications by Automatic Generation of Observers
Electronic Notes in Theoretical Computer Science (ENTCS)
| Hi-index | 0.00 |
MARTE/CCSL specifications express chronological and causal relations on UML models. In a previous work, we proposed a mechanism to verify Esterel implementations against MARTE/CCSL specifications. The mechanism was thought to be general enough to be extended to other languages. However, preserving the polychronous semantics of CCSL was pretty easy with a synchronous language but is much harder when the target language does not directly support coincidence/simultaneity. We show here how coincidence can be encoded. The process is illustrated using VHDL