A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proof, language, and interaction
Information and Computation
Coping with Latency in SOC Design
IEEE Micro
Some Synchronization Issues When Designing Embedded Systems from Components
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
A Protocol for Loosely Time-Triggered Architectures
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Concurrency in Synchronous Systems
ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
Proceedings of the 4th ACM international conference on Embedded software
Latency-insensitive design
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal Refinement Checking in a System-level Design Methodology
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Synchronization after design refinements with sensitive delay elements
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Step coverability algorithms for communicating systems
Science of Computer Programming
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Synchronous specifications are appealing in the design of large scale hardware and software systems because of their properties that facilitate verification and synthesis.When the target architecture is a distributed system, implementing a synchronous specification as a synchronous design may be inefficient in terms of both size (memory for software implementations or area for hardware implementations) and performance. A more elaborate implementation style where the basic synchronous paradigm is adapted to distributed architectures by introducing elements of asynchrony is, hence, highly desirable. Building on the tagged-signal model, we present a modeling for the distributed deployment of synchronous design. We offer a comparative exposition of various design approaches (synchronous, asynchronous, GALS, latency-insensitive, and synchronous programming) and we provide some insight on the role of signal absence in modeling synchronization in distributed concurrent systems. Finally, we compare two distinct methodologies, desynchronization and latency-insensitive design, and we elaborate on possible options to combine their results.