Communicating sequential processes
Communicating sequential processes
Synchronous programming with events and relations: the SIGNAL language and its semantics
Science of Computer Programming
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Implementation of the data-flow synchronous language SIGNAL
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
The B-book: assigning programs to meanings
The B-book: assigning programs to meanings
Interaction categories and the foundations of typed concurrent programming
Proceedings of the NATO Advanced Study Institute on Deductive program design
Science of Computer Programming
System Design with SystemC
The Theory and Practice of Concurrency
The Theory and Practice of Concurrency
Readings in Hardware/Software Co-Design
Readings in Hardware/Software Co-Design
Synthesis of Discrete-Event Controllers Based on the SignalEnvironment
Discrete Event Dynamic Systems
Co-inductive Axiomatization of a Synchronous Language
Proceedings of the 11th International Conference on Theorem Proving in Higher Order Logics
An ML-Like Module System for the Synchronous Language SIGNAL
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
A Protocol for Loosely Time-Triggered Architectures
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Polychrony for Formal Refinement-Checking in a System-Level Design Methodology
ACSD '03 Proceedings of the Third International Conference on Application of Concurrency to System Design
Synchronous Modeling of Avionics Applications using the SIGNAL Language
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
An Environment for Dynamic Component Composition for Efficient Co-Design
Proceedings of the conference on Design, automation and test in Europe
A Behavioral Type Inference System for Compositional System-on-Chip Design
ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Framework for Modeling the Distributed Deployment of Synchronous Designs
Formal Methods in System Design
A compositional behavioral modeling framework for embedded system design and conformance checking
International Journal of Parallel Programming
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Toward polychronous analysis and validation for timed software architectures in AADL
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring system architectures in AADL via Polychrony and SynDEx
Frontiers of Computer Science: Selected Publications from Chinese Universities
Polychronous modeling, analysis, verification and simulation for timed software architectures
Journal of Systems Architecture: the EUROMICRO Journal
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Rising complexity, increasing performance requirements, and shortening time-to-market demands necessitate newer design paradigms for embedded system design. Such newer design methodologies require raising the level of abstraction for design entry, reuse of intellectual property blocks as virtual components, refinement based design, and formal verification to prove correctness of refinement steps. The problem of combining various components from different designers and companies, designed at different levels of abstraction, and embodying heterogeneous models of computation is a difficult challenge for the designer community today. Moreover, one of the gating factors for widespread adoption of the system-level design paradigm is the lack of formal models, method and tools to support refinement. In the absence of provably correct and adequate behavioral synthesis techniques, the refinement of a system-level description towards its implementation is primarily a manual process. Furthermore, proving that the implementation preserves the properties of the higher system-level design-abstraction is an outstanding problem. In this paper, we address these issues and define a formal refinement-checking methodology for system-level design. Our methodology is based on a polychronous model of computation of the multi-clocked synchronous formalism SIGNAL. This formalism is implemented in the POLYCHRONY workbench. We demonstrate the effectiveness of our approach by the experimental case study of a SPECC modeling example. First, we define a technique to systematically model SPECC programs in the signal formalism. Second, we define a methodology to compare system-level models of SPECC programs and to validate behavioral equivalence relations between these models at different levels of abstraction. Although we use SPECC modeling examples to illustrate our technique, our methodology is generic and language-independent and the model that supports it conceptually minimal by offering a scalable notion and a flexible degree of abstraction.