Toward polychronous analysis and validation for timed software architectures in AADL

Authors:
Yue Ma;Huafeng Yu;Thierry Gautier;Paul Le Guernic;Jean-Pierre Talpin;Loïc Besnard;Maurice Heitz
Affiliations:
INRIA Rennes, Rennes Cedex, France;INRIA Rennes, Rennes Cedex, France;INRIA Rennes, Rennes Cedex, France;INRIA Rennes, Rennes Cedex, France;INRIA Rennes, Rennes Cedex, France;IRISA/CNRS, Rennes Cedex, France;Communication & Systems (C-S), Toulouse Cedex, France
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

Citing 11
Cited 2

Validation of Mixed SIGNAL-ALPHA Real-Time Systems through Affine Calculus on Clock Synchronisation Constraints

FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume II
Scheduling and memory requirements analysis with AADL

Proceedings of the 2005 annual ACM SIGAda international conference on Ada: The Engineering of Correct and Reliable Software for Real-Time & Distributed Systems using Ada and Related Technologies
From the prototype to the final embedded system using the Ocarina AADL tool suite

ACM Transactions on Embedded Computing Systems (TECS)
Synchronous Modeling and Validation of Priority Inheritance Schedulers

FASE '09 Proceedings of the 12th International Conference on Fundamental Approaches to Software Engineering: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
Translating AADL into BIP - Application to the Verification of Real-Time Systems

Models in Software Engineering
System-level co-simulation of integrated avionics using polychrony

Proceedings of the 2011 ACM Symposium on Applied Computing
Safety, Dependability and Performance Analysis of Extended AADL Models

The Computer Journal
Formal semantics and analysis of behavioral AADL models in real-time maude

FMOODS'10/FORTE'10 Proceedings of the 12th IFIP WG 6.1 international conference and 30th IFIP WG 6.1 international conference on Formal Techniques for Distributed Systems
A Timing Model for Specifying Multi Clock Automotive Systems: The Timing Augmented Description Language V2

ICECCS '12 Proceedings of the 2012 IEEE 17th International Conference on Engineering of Complex Computer Systems
Formal Refinement Checking in a System-level Design Methodology

Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Challenges and new trends in probabilistic timing analysis

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

Exploring system architectures in AADL via Polychrony and SynDEx

Frontiers of Computer Science: Selected Publications from Chinese Universities
Polychronous modeling, analysis, verification and simulation for timed software architectures

Journal of Systems Architecture: the EUROMICRO Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

High-level architecture modeling languages, such as Architecture Analysis & Design Language (AADL), are gradually adopted in the design of embedded systems so that design choice verification, architecture exploration, and system property checking are carried out as early as possible. This paper presents our recent contributions to cope with clock-based timing analysis and validation of software architectures specified in AADL. In order to avoid semantics ambiguities of AADL, we mainly consider the AADL features related to real-time and logical time properties. We endue them with a semantics in the polychronous model of computation; this semantics is quickly reviewed. The semantics enables timing analysis, formal verification and simulation. In addition, thread-level scheduling, based on affine clock relations is also briefly presented here. A tutorial avionic case study, provided by C-S, has been adopted to illustrate our overall contribution.