Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Implementation of the data-flow synchronous language SIGNAL
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Synthesis of Discrete-Event Controllers Based on the SignalEnvironment
Discrete Event Dynamic Systems
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume II
Scheduling and memory requirements analysis with AADL
Proceedings of the 2005 annual ACM SIGAda international conference on Ada: The Engineering of Correct and Reliable Software for Real-Time & Distributed Systems using Ada and Related Technologies
Virtual execution of AADL models via a translation into synchronous programs
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
From the prototype to the final embedded system using the Ocarina AADL tool suite
ACM Transactions on Embedded Computing Systems (TECS)
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Synchronous Modeling and Validation of Priority Inheritance Schedulers
FASE '09 Proceedings of the 12th International Conference on Fundamental Approaches to Software Engineering: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
CADP 2006: a toolbox for the construction and analysis of distributed processes
CAV'07 Proceedings of the 19th international conference on Computer aided verification
System-level co-simulation of integrated avionics using polychrony
Proceedings of the 2011 ACM Symposium on Applied Computing
Safety, Dependability and Performance Analysis of Extended AADL Models
The Computer Journal
Formal semantics and analysis of behavioral AADL models in real-time maude
FMOODS'10/FORTE'10 Proceedings of the 12th IFIP WG 6.1 international conference and 30th IFIP WG 6.1 international conference on Formal Techniques for Distributed Systems
ICECCS '12 Proceedings of the 2012 IEEE 17th International Conference on Engineering of Complex Computer Systems
Formal Refinement Checking in a System-level Design Methodology
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Toward polychronous analysis and validation for timed software architectures in AADL
Proceedings of the Conference on Design, Automation and Test in Europe
Challenges and new trends in probabilistic timing analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 0.00 |
High-level modeling languages and standards, such as Simulink, SysML, MARTE and AADL (Architecture Analysis & Design Language), are increasingly adopted in the design of embedded systems so that system-level analysis, verification and validation (V&V) and architecture exploration are carried out as early as possible. This paper presents our main contribution in this aim by considering embedded systems architectural modeling in AADL and functional modeling in Simulink; an original clock-based timing analysis and validation of the overall system is achieved via a formal polychronous/multi-clock model of computation. In order to avoid semantics ambiguities of AADL and Simulink, their features related to real-time and logical time properties are first studied. We then endue them with a semantics in the polychronous model of computation. We use this model of computation to jointly analyze the non-functional real-time and logical-time properties of the system (by means of logical and affine clock relations). Our approach demonstrates, through several case-studies conducted with Airbus and C-S Toulouse in the European projects CESAR and OPEES, how to cope with the system-level timing verification and validation of high-level AADL and Simulink components in the framework of Polychrony, a synchronous modeling framework dedicated to the design of safety-critical embedded systems.