Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
A Compositional Rule for Hardware Design Refinement
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
You Assume, We Guarantee: Methodology and Case Studies
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal Refinement Checking in a System-level Design Methodology
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
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The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of Intellectual Properties. Latency insensitive designs are synchronous distributed systems and are realized by assembling functional modules exchanging data on communication channels according to an appropriate protocol. The goal of the protocol is to guarantee that latency insensitive designs composed of functionally correct modules, behave correctly independently of the wire delays. A latency-insensitive protocol is presented that makes use of relay stations buffering signals propagating along long wires. To guarantee correct behavior of the overall system, modules must satisfy weak conditions. The weakness of the conditions makes our method widely applicable.