Leap scratchpads: automatic memory and cache management for reconfigurable logic

Authors:
Michael Adler;Kermin E. Fleming;Angshuman Parashar;Michael Pellauer;Joel Emer
Affiliations:
Intel Corporation, Hudson, MA, USA;Massachusetts Institute of Technology, Cambridge, MA, USA;Intel Corporation, Hudson, MA, USA;Massachusetts Institute of Technology, Cambridge, MA, USA;Intel Corporation, Hudson, MA, USA
Venue:
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2011

Citing 9
Cited 5

Achieving high instruction cache performance with an optimizing compiler

ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Cooperative prefetching: compiler and hardware support for effective instruction prefetching in modern processors

MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Stream-Oriented FPGA Computing in the Streams-C High Level Language

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk

MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
High-Level Language Abstraction for Reconfigurable Computing

Computer
Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary

ECOOP '08 Proceedings of the 22nd European conference on Object-Oriented Programming
Declarative aspects of memory management in the concurrent collections parallel programming model

Proceedings of the 4th workshop on Declarative aspects of multicore programming
Soft connections: addressing the hardware-design modularity problem

Proceedings of the 46th Annual Design Automation Conference
Designing hardware with dynamic memory abstraction

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

CoRAM: an in-fabric memory architecture for FPGA-based computing

Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Leveraging latency-insensitivity to ease multiple FPGA design

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
And then there were none: a stall-free real-time garbage collector for reconfigurable hardware

Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
And then there were none: a stall-free real-time garbage collector for reconfigurable hardware

Communications of the ACM

Quantified Score

Hi-index	0.02

Visualization

Abstract

Developers accelerating applications on FPGAs or other reconfigurable logic have nothing but raw memory devices in their standard toolkits. Each project typically includes tedious development of single-use memory management. Software developers expect a programming environment to include automatic memory management. Virtual memory provides the illusion of very large arrays and processor caches reduce access latency without explicit programmer instructions. LEAP scratchpads for reconfigurable logic dynamically allocate and manage multiple, independent, memory arrays in a large backing store. Scratchpad accesses are cached automatically in multiple levels, ranging from shared on-board, RAM-based, set-associative caches to private caches stored in FPGA RAM blocks. In the LEAP framework, scratchpads share the same interface as on-die RAM blocks and are plug-in replacements. Additional libraries support heap management within a storage set. Like software developers, accelerator authors using scratchpads may focus more on core algorithms and less on memory management.