Hardware/software co-simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
A reconfigurable logic machine for fast event-driven simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cut-based functional debugging for programmable systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A transaction-based unified simulation/emulation architecture for functional verification
Proceedings of the 38th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Principles of VERILOG PLI
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
Speeding Up Hardware Prototyping by Incremental Simulation/Emulation
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
Improving the observability and controllability of datapaths for emulation-based debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Fast co-verification of HDL models
Microelectronic Engineering
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A method for simulation-emulation co-operation of Verilog and VHDL models is presented. The method is based on using Programming Language Interface (PLI) to achieve speedup in prototyping and to facilitate the communication between an emulator and a simulator. The PLI technique is implemented for both Verilog and VHDL models. The results show that this simulation-emulation co-operation method can significantly reduce the simulation time of a design implemented by VHDL codes as well as Verilog codes.