Prospects for WSI: A Manufacturing Perspective
Computer - Special issue on wafer-scale integration
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
AnyBoard: An FPGA-Based, Reconfigurable System
IEEE Design & Test
Configurable logic: a dynamically programmable cellular architecture and its vlsi implementation
Configurable logic: a dynamically programmable cellular architecture and its vlsi implementation
An Approach to Highly Integrated, Computer-Maintained Cellular Arrays
IEEE Transactions on Computers
IBM Journal of Research and Development
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The fine granularity and reconfigurable nature of field-programmable Gate Arrays (FPGA's) suggest that defect-tolerant methods can be readily applied to these devices in order to increase their maximum economic sizes, through increased yield. This paper identifies the inability to contain faults within single cells and the need for fast reconfiguration as the key obstacles to obtaining a significant increase in yield. Monte Carlo defect modeling of the photolithographic layers of VLSI FPGA's is used as a foundation for the yield modeling of various defect-tolerant architectures. Results suggest that a medium-grain architecture is the best solution, offering a substantial increase in size without significant side effects. This architecture is shown to produce greater gate densities than the alternative approach of realizing ultralarge scale FPGA's--multichip modules.