An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
Cost minimization of partitions into multiple devices
DAC '93 Proceedings of the 30th international Design Automation Conference
Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Partitioning with cone structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Performance-driven multi-FPGA partitioning using functional clustering and replication
DAC '98 Proceedings of the 35th annual Design Automation Conference
Generation of very large circuits to benchmark the partitioning of FPGA
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs
IEEE Design & Test
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In this paper, we present a new integrated synthesisand partitioning method for multiple-FPGA applications.This method first synthesizes a design specificationin a fine-grained way so that functional clusters can bepreserved based on the structural nature of the designspecification.Then, it applies a hierarchical set-coveringpartitioning method to form the final FPGA partitionings.Our approach bridges the gap between HDL synthesisand physical partitioning by fully exploiting the designhierarchy.Experimental results on a number of benchmarksand industrial designs demonstrate that I/O limitsare the bottleneck for CLB utilization when applying atraditional multiple-FPGA synthesis method on flattenednetlists.In contrast, by fully exploiting the design structuralhierarchy during the multiple-FPGA partitioning,our proposed method produces fewer FPGA partitionswith higher CLB and low I/O-pin utilizations.