High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
A tutorial on logic synthesis for lookup-table based FPGAs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Digital system design using field programmable gate arrays
Digital system design using field programmable gate arrays
Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Creating hierarchy in HDL-based high density FGPA design
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Module generation of complex macros for logic-emulation applications
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Multi-way FPGA partitioning by fully exploiting design hierarchy
DAC '97 Proceedings of the 34th annual Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
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This paper presents a study on the interaction between HDL synthesis and partitioning for multi-FPGA designs with varying structural characteristics and HDL coding styles. We propose an integrated synthesis and partitioning methodology for multi-FPGA designs and demonstrate that the proper use of integrated HDL synthesis and partitioning methods is crucial to achieving high density multi-FPGA designs.