A linear-time heuristic for improving network partitions
25 years of DAC Papers on Twenty-five years of electronic design automation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Re-engineering of timing constrained placements for regular architectures
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient multi-view design model for real-time interactive synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Motif Reference Manual B: for OSF/Motif Release 1.2
Motif Reference Manual B: for OSF/Motif Release 1.2
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
Emulation verification of the Motorola 68060
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Engineering change: methodology and applications to behavioral and system synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multiway FPGA partitioning by fully exploiting design hierarchy
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient error detection, localization, and correction for FPGA-based debugging
Proceedings of the 37th Annual Design Automation Conference
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In recent years, logic emulation has been widely usedas a key design verification methodology in many complex CPU, telecom, and multimedia design projects. When using logic emulation for design verification, designers often need toperform engineering changes as a result of design debugging of a design specificationmodification. One of the essential issues to engineeringchanges is the turn-around time. Ideally, after designers modify their designs, they resume their debugging and verification tasks immediately. However, converting a design from its Register-Transfer-Level (RTL) description to a target emulator is a time-consuming procedure which may take hours. Such long engineering-change turn-around times are unacceptable by the designers. In this paper, we present a real-time RTLengineering-change method supporting on-line debuggingfor logic-emulation applications. We propose a novel design method which is able to link design data generated at different design stages in a unified way. Using thismethod, the users can immediately locate the portion ofthe circuit design affected by the design modification fromits RTL specification. This feature provides users with afast time-to-debug environment by significantly improving the efficiency of the engineering-change process. We have developed aprototype system Quick ECO supporting interactive on-line RTL engineering changes. Experimental results on a number of industrial designs are reported to demonstrate the effectiveness of the proposed method.