ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Physical design CAD in deep sub-micron era
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Low overhead fault-tolerant FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Engineering change: methodology and applications to behavioral and system synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A case study of partially evaluated hardware circuits: Key-specific DES
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
FPGA synthesis for minimum area, delay and power
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hi-index | 0.02 |
Simulations for modern designs are often performed on Field Programmable Gate Array technology in a functional test and debugging process known as emulation, allowing for more complex simulations than possible in software. One drawback to emulation is the lengthy time spent in the back-end CAD tools for each debugging iteration, including debugging changes and the introduction of control and observation logic. We have developed a technique that confines the re-place-and-route area to only the portions of the design affected by the introduction of the test logic and by the debugging changes. Therefore, the back-end CAD effort for error detection, localization, and correction is reduced. This benefit is achieved by partitioning the design at the physical level into independent blocks, and the test logic and design changes are localized to the affected blocks. The result is a shortened time between debugging iterations, and thus a shortened time-to-market for the design.