Space-time scheduling of instruction-level parallelism on a raw machine
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
IEEE Transactions on Computers
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Interactive Ray Tracing Using a SIMD Reconfigurable Architecture
SBAC-PAD '02 Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing
Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Reconfigurable Parallel Computing Architecture for On-Board Data Processing
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the conference on Design, automation and test in Europe
Very wide register: an asymmetric register file organization for low power embedded processors
Proceedings of the conference on Design, automation and test in Europe
A medium-grain reconfigurable architecture for DSP: VLSI design, benchmark mapping, and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural modifications to enhance the floating-point performance of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
Floating-point FPGA: architecture and modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
With a huge increase in demand for various kinds of compute-intensive applications in electronic systems, researchers have focused on coarse-grained reconfigurable architectures because of their advantages: high performance and flexibility. This paper presents FloRA, a coarse-grained reconfigurable architecture with floating-point support. A two-dimensional array of integer processing elements in FloRA is configured at run-time to perform floating-point operations as well as integer operations. Fabricated using 130nm process, the total area overhead due to additional hardware for floating-point operations is about 7.4% compared to the previous architecture which does not support floating-point operations. The fabricated chip runs at 125MHz clock frequency and 1.2V power supply. Experiments show 11.6x speedup on average compared to ARM9 with a vector-floating-point unit for integer-only benchmark programs as well as programs containing floating-point operations. Compared with other similar approaches including XPP and Butter, the proposed architecture shows much higher performance for integer applications, while maintaining about half the performance of Butter for floating-point applications.