Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture

Authors:
Jürgen Becker;Thilo Pionteck;Christian Habermann;Manfred Glesner
Affiliations:
-;-;-;-
Venue:
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Year:
2001

Citing 0
Cited 10

A Framework for Teaching (Re)Configurable Architectures in Student Projects

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing

Proceedings of the 1st conference on Computing frontiers
Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Journal of VLSI Signal Processing Systems
Run-time reconfigurable systems for digital signal processing applications: a survey

Journal of VLSI Signal Processing Systems
A medium-grain reconfigurable architecture for DSP: VLSI design, benchmark mapping, and performance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A low-overhead interconnect architecture for virtual reconfigurable fabrics

Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
BPR: fast FPGA placement and routing using macroblocks

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Abstract: This paper presents the hardware structure and application of a coarse-grained dynamically reconfigurable hardware architecture dedicated to wireless communication systems. The application tailored architecture, called DReAM (Dynamically Reconfigurable Hardware Architecture for Mobile Communication Systems), is a research project at the Darmstadt University of Technology. It covers the complete design process from analyzing the requirements for the dedicated application field, the specification and VHDL implementation of the architecture, up to the physical layout for the final chip. In the following we provide an overview of the major design stages, starting with a motivation for choosing the concept of distributed arithmetic in reconfigurable computing.