Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing

Authors:
Tudor Murgan;Mihail Petrov;Mateusz Majer;Peter Zipf;Manfred Glesner;Ulrich Heinkel;Joerg Pleickhardt;Bernd Bleisteiner
Affiliations:
Darmstadt University of Technology, Darmstadt, Germany;Darmstadt University of Technology, Darmstadt, Germany;Darmstadt University of Technology, Darmstadt, Germany;Darmstadt University of Technology, Darmstadt, Germany;Darmstadt University of Technology, Darmstadt, Germany;Lucent Technologies Network Systems GmbH, Nürnberg, Germany;Lucent Technologies Network Systems GmbH, Nürnberg, Germany;Lucent Technologies Network Systems GmbH, Nürnberg, Germany
Venue:
Proceedings of the 1st conference on Computing frontiers
Year:
2004

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Abstract

The standardisation process of Optical Transport Networks generally spans a long period of time. For providers intending to be present early on the market, this implies costly design re-spins if the wrong "flavour" of the protocol standard has been implemented. Extending a protocol processing device through application specific reconfigurable elements or multiprocessor units augment its flexibility. Thus, the architecture can be upgraded to standard updates or changes not even considered at design time. This paper discusses several flexible architectural extensions for a complex ASIC for network processing device developed by Lucent Technologies Network Systems GmbH in Nürnberg. The device is a multi-rate multiple forward error correction code device which supports 40/43 Gbit/s applications. The proposed architectural enhancements provide adaptable overhead processing and include solutions based on reconfigurable elements, single processing units and multiprocessors.