PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
PipeRench implementation of the instruction path coprocessor
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Java Virtual Machine Specification
Java Virtual Machine Specification
Mapping Applications onto Reconfigurable Kress Arrays
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A Hardware Virtual Machine for the Networked Reconfiguration
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
Design Technology for Networked Reconfigurable FPGA Platforms
Proceedings of the conference on Design, automation and test in Europe
The Use of Runtime Configuration Capabilities for Networked Embedded Systems
Proceedings of the conference on Design, automation and test in Europe
Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
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Reconfigurable hardware will be used in many future embedded applications. Since most of these embedded systems will be temporarily or permanently connected to a network, the possibility to reload parts of the application at run time arises. In the 90ies it was recognized, that the huge variety of processors would lead to a tremendous amount of binaries for the same piece of software. For the hardware parts of an embedded system, the situation today is even worse. The java approach based on a java virtual machine (JVM) was invented to solve the problem for software. In this paper, we show how the hardware parts of an embedded system can be implemented in a hardware byte code, which can be interpreted using a virtual hardware machine running on an arbitrary FPGA. Our results show that this approach is feasible and that it leads to fast, portable and reconfigurable designs, which run on any programmable target architecture.