Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Trading conflict and capacity aliasing in conditional branch predictors
Proceedings of the 24th annual international symposium on Computer architecture
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The impact of delay on the design of branch predictors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Increasing processor performance by implementing deeper pipelines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design tradeoffs for the Alpha EV8 conditional branch predictor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Neural methods for dynamic branch prediction
ACM Transactions on Computer Systems (TOCS)
Predicting Conditional Branches With Fusion-Based Hybrid Predictors
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Reconsidering Complex Branch Predictors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Effective ahead pipelining of instruction block address generation
Proceedings of the 30th annual international symposium on Computer architecture
Proceedings of the 30th annual international symposium on Computer architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Improving branch prediction by understanding branch behavior
Improving branch prediction by understanding branch behavior
Picking Statistically Valid and Early Simulation Points
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Fast Path-Based Neural Branch Prediction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Toward kilo-instruction processors
ACM Transactions on Architecture and Code Optimization (TACO)
Piecewise Linear Branch Prediction
Proceedings of the 32nd annual international symposium on Computer Architecture
Analysis of the O-GEometric History Length Branch Predictor
Proceedings of the 32nd annual international symposium on Computer Architecture
Creating artificial global history to improve branch prediction accuracy
Proceedings of the 23rd international conference on Supercomputing
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The continual demand for greater performance and growing concerns about the power consumption in highperformance microprocessors make the branch predictor a critical component of modern microarchitectures. Recent research in applying machine learning techniques to the branch prediction problem has shown incredible improvements in branch prediction accuracy by exploiting correlations in very long branch histories. Nevertheless, these techniques have not been adopted by industry due to the high implementation complexity. In this paper, we propose a global-history Divideand- Conquer (gDAC) branch predictor that achieves IPC rates that are near that of the best neural predictors, but remains easy to implement because they only make use of simple tables of saturating counters. We show how to use ahead-pipelining to implement our gDAC predictor with a single-cycle effective latency. Our gDAC predictor achieves higher performance (IPC) than the original global history perceptron predictor across all predictor sizes evaluated, and outperforms the path-based neural predictor for predictors 16KB and larger. At 128KB, gDAC even achieves an IPC rate equal to the recently proposed piecewise-linear neural branch predictor.