Introduction to algorithms
Corpus-based static branch prediction
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Dynamic path-based branch correlation
Proceedings of the 28th annual international symposium on Microarchitecture
An analysis of correlation and predictability: what makes two-level branch predictors work
Proceedings of the 25th annual international symposium on Computer architecture
Variable length path branch prediction
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
The impact of delay on the design of branch predictors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Increasing processor performance by implementing deeper pipelines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design tradeoffs for the Alpha EV8 conditional branch predictor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Neural methods for dynamic branch prediction
ACM Transactions on Computer Systems (TOCS)
The Alpha 21264 Microprocessor
IEEE Micro
Predicting Conditional Branches With Fusion-Based Hybrid Predictors
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Hierarchical Scheduling Windows
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Reconsidering Complex Branch Predictors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Effective ahead pipelining of instruction block address generation
Proceedings of the 30th annual international symposium on Computer architecture
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic Branch Prediction with Perceptrons
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Prophet/Critic Hybrid Branch Prediction
Proceedings of the 31st annual international symposium on Computer architecture
Improved latency and accuracy for neural branch prediction
ACM Transactions on Computer Systems (TOCS)
Piecewise Linear Branch Prediction
Proceedings of the 32nd annual international symposium on Computer Architecture
Analysis of the O-GEometric History Length Branch Predictor
Proceedings of the 32nd annual international symposium on Computer Architecture
Merging path and gshare indexing in perceptron branch prediction
ACM Transactions on Architecture and Code Optimization (TACO)
A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Dynamic feature selection for hardware prediction
Journal of Systems Architecture: the EUROMICRO Journal
Long-latency branches: how much do they matter?
ACM SIGARCH Computer Architecture News
ReStore: Symptom-Based Soft Error Detection in Microprocessors
IEEE Transactions on Dependable and Secure Computing
Wide and efficient trace prediction using the local trace predictor
Proceedings of the 20th annual international conference on Supercomputing
Accurate branch prediction for short threads
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Generalizing neural branch prediction
ACM Transactions on Architecture and Code Optimization (TACO)
Low-power, high-performance analog neural branch prediction
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Branch Predictor Warmup for Sampled Simulation through Branch History Matching
Transactions on High-Performance Embedded Architectures and Compilers II
Dynamic branch prediction and control speculation
International Journal of High Performance Systems Architecture
Modulo path history for the reduction of pipeline overheads in path-based neural branch predictors
International Journal of Parallel Programming
The combined perceptron branch predictor
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Improving accuracy of perceptron predictor through correlating data values in SMT processors
ISNN'05 Proceedings of the Second international conference on Advances in Neural Networks - Volume Part III
A new case for the TAGE branch predictor
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the ACM International Conference on Computing Frontiers
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Microarchitectural prediction based on neural learninghas received increasing attention in recent years. However,neural prediction remains impractical because its superioraccuracy over conventional predictors is not enough to offsetthe cost imposed by its high latency. We present a newneural branch predictor that solves the problem from bothdirections: it is both more accurate and much faster thanprevious neural predictors. Our predictor improves accuracyby combining path and pattern history to overcomelimitations inherent to previous predictors. It also has muchlower latency than previous neural predictors. The result isa predictor with accuracy far superior to conventional predictorsbut with latency comparable to predictors from industrialdesigns. Our simulations show that a path-basedneural predictor improves the instructions-per-cycle (IPC)rate of an aggressively clocked microarchitecture by 16%over the original perceptron predictor.