Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Evidence-based static branch prediction using machine learning
ACM Transactions on Programming Languages and Systems (TOPLAS)
Neural methods for dynamic branch prediction
ACM Transactions on Computer Systems (TOCS)
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Control-Flow Speculation through Value Prediction
IEEE Transactions on Computers
Fast Path-Based Neural Branch Prediction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
First Step to Combining Control and Data Speculation
IWIA '98 Proceedings of the 1998 International Workshop on Innovative Architecture
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Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle. With the pipeline deepen and issue widths increase, the branch predictor plays a more important role in improving the performance of an SMT processor. Many predictors based on neural network, especially on perceptron, are proposed to provide a more accurate dynamic branch prediction than before in the literature. In this paper, we propose an effective method to improve the accuracy of a perceptron predictor through correlating data values in SMT processors. The key idea is using a dynamic bias input, which comes from some information independent on the branch histories (data values for example), to realize the objective of improving accuracy. The implementation of our method is simple, and the predicting latency is not lengthened. Execution-driven simulation results show that our method works successfully on improving the accuracy of a perceptron predictor and increasing the overall instruction throughput of SMT processors.