Alternative implementations of two-level adaptive branch prediction
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The effect of speculatively updating branch history on branch prediction accuracy, revisited
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Alternative implementations of hybrid branch predictors
Proceedings of the 28th annual international symposium on Microarchitecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Analysis of branch prediction via data compression
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Assigning confidence to conditional branch predictions
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
An analysis of correlation and predictability: what makes two-level branch predictors work
Proceedings of the 25th annual international symposium on Computer architecture
Confidence estimation for speculation control
Proceedings of the 25th annual international symposium on Computer architecture
Dynamic history-length fitting: a third level of adaptivity for branch prediction
Proceedings of the 25th annual international symposium on Computer architecture
The YAGS branch prediction scheme
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Variable length path branch prediction
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
A scalable front-end architecture for fast instruction delivery
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
The impact of delay on the design of branch predictors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Increasing processor performance by implementing deeper pipelines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design tradeoffs for the Alpha EV8 conditional branch predictor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Neural methods for dynamic branch prediction
ACM Transactions on Computer Systems (TOCS)
Predicting Conditional Branches With Fusion-Based Hybrid Predictors
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Keynote: Is there anything more to learn about high performance processors?
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Reconsidering Complex Branch Predictors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Effective ahead pipelining of instruction block address generation
Proceedings of the 30th annual international symposium on Computer architecture
The Effects of Mispredicted-Path Execution on Branch Prediction Structures
PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference
PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Fast Path-Based Neural Branch Prediction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Control Flow Optimization Via Dynamic Reconvergence Prediction
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Improving branch prediction accuracy with parallel conservative correctors
Proceedings of the 2nd conference on Computing frontiers
Piecewise Linear Branch Prediction
Proceedings of the 32nd annual international symposium on Computer Architecture
Dynamic feature selection for hardware prediction
Journal of Systems Architecture: the EUROMICRO Journal
Long-latency branches: how much do they matter?
ACM SIGARCH Computer Architecture News
Wide and efficient trace prediction using the local trace predictor
Proceedings of the 20th annual international conference on Supercomputing
OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems
IEEE Transactions on Computers
Fairness and Throughput in Switch on Event Multithreading
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Fairness enforcement in switch on event multithreading
ACM Transactions on Architecture and Code Optimization (TACO)
Generalizing neural branch prediction
ACM Transactions on Architecture and Code Optimization (TACO)
Service level agreement for multithreaded processors
ACM Transactions on Architecture and Code Optimization (TACO)
Dynamic branch prediction and control speculation
International Journal of High Performance Systems Architecture
The combined perceptron branch predictor
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
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This paper introduces the prophet/critic hybrid conditionalbranch predictor, which has two component predictorsthat play the role of either prophet or critic.Theprophet is a conventional predictor that uses branch historyto predict the direction of the current branch.Further accessesof the prophet yield predictions for the branches followingthe current one.Predictions for the current branchand the ones that follow are collectively known as thebranch's future.They are actually a prophecy, or predictedbranch future.The critic uses both the branch's history andfuture to give a critique of the prophet's prediction fo thecurrent branch.The critique, either agree or disagree, isused to generate the final prediction for the branch.Our results show an 8K + 8K byte prophet/critic hybridhas 39% fewer mispredicts than a 16K byte 2Bc-gskewpredictor-a predictor similar to that of the proposed Compaq*Alpha* EV8 processor-across a wide range of applications.The distance between pipeline flushes due to mispredictsincreases from one flush per 418 micro-operations(uops) to one per 680 uops.For gcc, the percentage of mispredictedbranches drops from 3.11% to 1.23%.On a machinebased on the Intel® Pentium® 4 processor, this improvesuPC (Uops Per Cycle) by 7.8% (18% for gcc) andreduces the number of uops fetched (along both correct andincorrect paths) by 8.6%.