Alternative implementations of two-level adaptive branch prediction
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Increasing the instruction fetch rate via multiple branch prediction and a branch address cache
ICS '93 Proceedings of the 7th international conference on Supercomputing
Analysis of branch prediction via data compression
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Assigning confidence to conditional branch predictions
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Trading conflict and capacity aliasing in conditional branch predictors
Proceedings of the 24th annual international symposium on Computer architecture
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
An analysis of correlation and predictability: what makes two-level branch predictors work
Proceedings of the 25th annual international symposium on Computer architecture
Dynamic history-length fitting: a third level of adaptivity for branch prediction
Proceedings of the 25th annual international symposium on Computer architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The YAGS branch prediction scheme
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Improving branch predictors by correlating on data values
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Completion time multiple branch prediction for enhancing trace cache performance
Proceedings of the 27th annual international symposium on Computer architecture
The impact of delay on the design of branch predictors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Design tradeoffs for the Alpha EV8 conditional branch predictor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Keynote: Is there anything more to learn about high performance processors?
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic Branch Prediction with Perceptrons
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Power Issues Related to Branch Prediction
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Prophet/Critic Hybrid Branch Prediction
Proceedings of the 31st annual international symposium on Computer architecture
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In this paper we discuss how a confidence mechanism is integrated into the branch prediction correctors to improve the accuracy of a primary predictor in the prediction process. A corrector reverses the decision of the primary predictor when it is confident that the primary predictor may be wrong. Using correctors to improve prediction accuracy is efficient because correctors only need to remember the information on branches that the primary predictor has problems with. Each corrector maintains its own "confidence" value. In our proposed design, these confidence values are judged conservatively so that a corrector will only reverse the predicted direction of the primary predictor when it is confident about the reversal. Moreover, to further increase the accuracy of the prediction, we use multiple correctors working together, each having a particular "expertise". In this paper we present three correctors: the interval corrector, the bimodal corrector, and the two-level corrector. Simulation experiments on a common evaluation framework show that correctors with an additional 2 KB (i.e., 8 KB totally) of storage can reduce mis-predicted branches by 18% over a primary predictor that has only 6 KB of storage. The total prediction accuracy of this 8 KB predictor is 28.4% better than a Gshare predictor with the same size. We also discuss some design issues such as the critical path and show how correctors can be easily implemented into these designs