Race-free interconnection networks and multiprocessor consistency
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Automatable verification of sequential consistency
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Variability in Architectural Simulations of Multi-Threaded Workloads
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Scalable Hardware Memory Disambiguation for High ILP Processors
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Reducing Design Complexity of the Load/Store Queue
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
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Value-based replay eliminates the need for content-addressable memories in the load queue, removing one barrier to scalable outof-order instruction windows. Instead, correct memory ordering is maintained by simply re-executing certain load instructions in program order. A set of novel filtering heuristics reduces the average additional cache bandwidth demanded by value-based replay to less than 3.5 percent.