Critical issues regarding HPS, a high performance microarchitecture

Authors:
Y. N. Patt;S. W. Melvin;W. M. Hwu;M. C. Shebanow
Affiliations:
Computer Science Diuiaion, University of Calqornia, Berkeley, Berkeley, CA;Computer Science Diuiaion, University of Calqornia, Berkeley, Berkeley, CA;Computer Science Diuiaion, University of Calqornia, Berkeley, Berkeley, CA;Computer Science Diuiaion, University of Calqornia, Berkeley, Berkeley, CA
Venue:
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
Year:
1985

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Abstract

HPS is a new model for a high performance microarchitecture which is targeted for implementing very dissimilar ISP architectures. It derives its performance from executing the operations within a restricted window of a program out-of-order, asynchronously, and concurrently whenever possible. Before the model can be reduced to an effective working implementation of a particular target architecture, several issues need to be resolved. This paper discusses these issues, both in general and in the context of architectures with specific characteristics.