A power-efficient and scalable load-store queue design

Authors:
Fernando Castro;Daniel Chaver;Luis Pinuel;Manuel Prieto;Michael C. Huang;Francisco Tirado
Affiliations:
ArTeCS Group, Complutense University of Madrid, Madrid, Spain;ArTeCS Group, Complutense University of Madrid, Madrid, Spain;ArTeCS Group, Complutense University of Madrid, Madrid, Spain;ArTeCS Group, Complutense University of Madrid, Madrid, Spain;University of Rochester, Rochester, New York;ArTeCS Group, Complutense University of Madrid, Madrid, Spain
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.