IATAC: a smart predictor to turn-off L2 cache lines
ACM Transactions on Architecture and Code Optimization (TACO)
Skewed caches from a low-power perspective
Proceedings of the 2nd conference on Computing frontiers
Variable-Based Multi-module Data Caches for Clustered VLIW Processors
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 20th annual international conference on Supercomputing
A leakage-energy-reduction technique for cache memories in embedded processors
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Low Vccmin fault-tolerant cache with highly predictable performance
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Hot-and-Cold: using criticality in the design of energy-efficient caches
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches
Proceedings of the great lakes symposium on VLSI
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This paper investigates some power efficient data cache designsthat try to significantly reduce the cache energy consumption, bothstatic and dynamic, with a minimal impact in performance. The basicidea is to combine different threshold voltages with differentcache organizations that provide different levels of performance.Multi-banked organizations in combination with different approachesto allocate data to cache banks are explored. Some of the resultingcache architectures are shown to provide a good tradeoff betweenpower and performance.