Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Proceedings of the 43rd annual Design Automation Conference
An IC manufacturing yield model considering intra-die variations
Proceedings of the 43rd annual Design Automation Conference
Process variation aware OPC with variational lithography modeling
Proceedings of the 43rd annual Design Automation Conference
Standard cell characterization considering lithography induced variations
Proceedings of the 43rd annual Design Automation Conference
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
A Design Model for Random Process Variability
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
The impact of BEOL lithography effects on the SRAM cell performance and yield
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Variability aware modeling of SoCs: From device variations to manufactured system yield
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defocus-Aware Leakage Estimation and Control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Rethinking memory redundancy: optimal bit cell repair for maximum-information storage
Proceedings of the 48th Design Automation Conference
Maximum-information storage system: concept, implementation and application
Proceedings of the International Conference on Computer-Aided Design
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations
Proceedings of the 50th Annual Design Automation Conference
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Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. We present a computational framework, referred to as "Virtual SRAM Fab", for analyzing and estimating pre-Si SRAM array manufacturing yield considering both lithographic and electrical variations. The framework is being demonstrated for SRAM design/optimization in 45nm nodes and currently being used for both 32nm and 22nm technology nodes. The application and merit of the framework are illustrated using two different SRAM cells in a 45nm PD/SOI technology, which have been designed for similar stability/performance, but exhibit different parametric yields due to layout/lithographic variations. We also demonstrate the application of Virtual SRAM Fab for prediction of layout-induced imbalance in an 8T cell, which is a popular candidate for SRAM implementation in 32-22nm technology nodes.