Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
Convex Optimization
Digital Image Processing (3rd Edition)
Digital Image Processing (3rd Edition)
Elements of Information Theory (Wiley Series in Telecommunications and Signal Processing)
Elements of Information Theory (Wiley Series in Telecommunications and Signal Processing)
Proceedings of the 43rd annual Design Automation Conference
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Numerical Recipes 3rd Edition: The Art of Scientific Computing
Numerical Recipes 3rd Edition: The Art of Scientific Computing
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
SRAM parametric failure analysis
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 2009 International Conference on Computer-Aided Design
Adaptive sampling for efficient failure probability analysis of SRAM cells
Proceedings of the 2009 International Conference on Computer-Aided Design
Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Proceedings of the 2009 International Conference on Computer-Aided Design
Applications of the Signal Space Separation Method
IEEE Transactions on Signal Processing
Generalized Entropy Power Inequalities and Monotonicity Properties of Information
IEEE Transactions on Information Theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Rethinking memory redundancy: optimal bit cell repair for maximum-information storage
Proceedings of the 48th Design Automation Conference
Unequal-error-protection codes in SRAMs for mobile multimedia applications
Proceedings of the International Conference on Computer-Aided Design
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The aggressive technology scaling has made it increasingly difficult to design high-performance, high-density SRAM circuits. In this paper, we propose a new SRAM design methodology that is referred to as maximum-information storage system (MISS). Unlike most traditional SRAM circuits that are designed for maximum cell density, MISS aims to maximize the information density (i.e., the number of information bits per unit area). Towards this goal, an information model is derived to quantitatively measure the information bits stored in a given SRAM system. In addition, a convex optimization framework is developed to optimize SRAM cells to achieve maximum information storage. Our design example in a commercial 65nm CMOS process demonstrates that MISS achieves more than 3.5x area reduction over the traditional SRAM design, while storing the same amount of information. Furthermore, two real-life signal processing examples show that given the same area constraint, MISS can increase signal-to-noise ratio by more than 30 dB compared to the traditional SRAM system.