Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Convex Optimization
Variability in sub-100nm SRAM designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe
Parameterized macromodeling for analog system-level design exploration
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A holistic approach for statistical SRAM analysis
Proceedings of the 47th Design Automation Conference
A statistical simulation method for reliability analysis of SRAM core-cells
Proceedings of the 47th Design Automation Conference
Efficient SRAM failure rate prediction via Gibbs sampling
Proceedings of the 48th Design Automation Conference
Rethinking memory redundancy: optimal bit cell repair for maximum-information storage
Proceedings of the 48th Design Automation Conference
Unequal-error-protection codes in SRAMs for mobile multimedia applications
Proceedings of the International Conference on Computer-Aided Design
Maximum-information storage system: concept, implementation and application
Proceedings of the International Conference on Computer-Aided Design
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations
Proceedings of the 50th Annual Design Automation Conference
Modeling and design exploration of FBDRAM as on-chip memory
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
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With aggressive technology scaling, SRAM design has been seriously challenged by the difficulties in analyzing rare failure events. In this paper we propose to create statistical performance models with accuracy sufficient to facilitate probability extraction for SRAM parametric failures. A piecewise modeling technique is first proposed to capture the performance metrics over the large variation space. A controlled sampling scheme and a nested Monte Carlo analysis method are then applied for the failure probability extraction at cell-level and array-level respectively. Our 65nm SRAM example demonstrates that by combining the piecewise model and the fast probability extraction methods, we have significantly accelerated the SRAM failure analysis.