Remembrance of circuits past: macromodeling by data mining in large analog design spaces
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Efficient description of the design space of analog circuits
Proceedings of the 40th annual Design Automation Conference
Convex Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design
Proceedings of the 42nd annual Design Automation Conference
Variational interconnect analysis via PMTBR
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Poor man's TBR: a simple model reduction scheme
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SRAM parametric failure analysis
Proceedings of the 46th Annual Design Automation Conference
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In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our proposed approach captures a significantly larger analog design space to facilitate system-level design exploration. Combining a novel piece-wise approximation algorithm and a new multi-point model-order-reduction approach, the proposed method generates compact macromodels covering the entire feasible design space. Our experiments demonstrate that using such models can achieve more than 60 x speed-up while incurring less than 4% overall error when varying design parameters by an order of magnitude.