Proceedings of the 39th annual Design Automation Conference
Design of pipeline analog-to-digital converters via geometric programming
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automated Optimal Design of Switched-Capacitor Filters
Proceedings of the conference on Design, automation and test in Europe
Convex Optimization
Synthesis of high-performance analog circuits in ASTRX/OBLX
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Deterministic approaches to analog performance space exploration (PSE)
Proceedings of the 42nd annual Design Automation Conference
Performance-centering optimization for system-level analog design exploration
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Proceedings of the 43rd annual Design Automation Conference
Digital Circuit Optimization via Geometric Programming
Operations Research
Parameterized macromodeling for analog system-level design exploration
Proceedings of the 44th annual Design Automation Conference
| Hi-index | 0.00 |
In this paper we present a method for determining the feasible set of analog design problems and we propose an efficient method for their verification. The verification method presented relies on the formulation of the analog circuit design problem as a convex optimization problem in both the design variables and the performance specifications. Since the design is convex not only in the design variables but also in the specification parameters, we observe that the feasible sets are convex and points at the boundary can be found by solving a single convex optimization problem. We also show that feasible sets can be very well approximated with a polyhedron and therefore defined by a finite set of points. The implication of the latter is that new verifications do not need to be run for every new instantiation of a synthesized analog cell.