Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A methodology for statistical estimation of read access yield in SRAMs
Proceedings of the 45th annual Design Automation Conference
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Efficient design-specific worst-case corner extraction for integrated circuits
Proceedings of the 46th Annual Design Automation Conference
SRAM parametric failure analysis
Proceedings of the 46th Annual Design Automation Conference
Adaptive sampling for efficient failure probability analysis of SRAM cells
Proceedings of the 2009 International Conference on Computer-Aided Design
A fast estimation of SRAM failure rate using probability collectives
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Yield estimation via multi-cones
Proceedings of the 49th Annual Design Automation Conference
Classifying circuit performance using active-learning guided support vector machines
Proceedings of the International Conference on Computer-Aided Design
Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling
Proceedings of the Conference on Design, Automation and Test in Europe
Cross entropy minimization for efficient estimation of SRAM failure rate
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Scalable and efficient analog parametric fault identification
Proceedings of the International Conference on Computer-Aided Design
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Statistical analysis of SRAM has emerged as a challenging issue because the failure rate of SRAM cells is extremely small. In this paper, we develop an efficient importance sampling algorithm to capture the rare failure event of SRAM cells. In particular, we adapt the Gibbs sampling technique from the statistics community to find the optimal probability distribution for importance sampling with minimum computational cost (i.e., a small number of transistor-level simulations). The proposed Gibbs sampling method applies an integrated optimization engine to adaptively explore the failure region by sampling a sequence of one-dimensional probability distributions. Several implementation issues such as one-dimensional random sampling and starting point selection are carefully studied to make the Gibbs sampling method efficient and accurate for SRAM failure rate prediction. Our experimental results of a commercial 65nm SRAM cell demonstrate that the proposed Gibbs sampling method achieves 3~10x runtime speed-up over other state-of-the-art techniques without surrendering any accuracy.