Parametric fault simulation and test vector generation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Test Metrics for Analog Parametric Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integrated approach for analog circuit testing with a minimum number of detected parameters
ITC'94 Proceedings of the 1994 international conference on Test
Efficient SRAM failure rate prediction via Gibbs sampling
Proceedings of the 48th Design Automation Conference
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis
Proceedings of the International Conference on Computer-Aided Design
Goal-oriented stimulus generation for analog circuits
Proceedings of the 49th Annual Design Automation Conference
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Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be identified. This paper proposes an iterative sampling method to identify these faults in large-scale analog circuits with a constrained simulation budget. Experiment results on two circuits from a serial IO interface demonstrate the effectiveness of the methodology. The proposed method identifies a significantly larger and diverse set of critical parametric faults compared to a Monte Carlo-based approach for identical computational budget, particularly for cases involving significant process variations.