Variability aware modeling of SoCs: From device variations to manufactured system yield

Authors:
M. Miranda;B. Dierickx;P. Zuber;P. Dobrovoln;F. Kutscherauer;P. Roussel;P. Poliakov
Affiliations:
IMEC Kapeldreef 75, 3001 Leuven, Belgium;IMEC Kapeldreef 75, 3001 Leuven, Belgium;IMEC Kapeldreef 75, 3001 Leuven, Belgium;IMEC Kapeldreef 75, 3001 Leuven, Belgium;IMEC Kapeldreef 75, 3001 Leuven, Belgium;IMEC Kapeldreef 75, 3001 Leuven, Belgium;IMEC Kapeldreef 75, 3001 Leuven, Belgium
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

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Abstract

As CMOS technology feature sizes decrease, random within-die and inter-die process variations more and more jeopardize SoC parametric and functional yield. Largely neglected in the State-Of-the-Art, dynamic energy consumption and power dissipation becomes heavily affected. This paper describes a technique to systematically bring statistically correlated timing/energy variations all the way up from the device to the SoC level. We propose a flow for Variability Aware Modeling (VAM) and apply it to a case study using a industrial test vehicle.