Robust gate sizing via mean excess delay minimization
Proceedings of the 2008 international symposium on Physical design
Linear analysis of random process variability
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Proceedings of the 2009 International Conference on Computer-Aided Design
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A new approach to analyze process variation through measured current variation is introduced. The methodology concludes with a simple and convenient posynomial model for random process variability to bridge the gap between existingstatistical methods and circuit design. The model contains only design variables: transistor sizes W and L, and operating points Vgs and Vds. Modeling random process variability in this way allows for adaptability to optimization problems, time efficient methods for gathering statistical information in comparison to Monte Carlo, and analternative equation for hand analysis.