Linear analysis of random process variability

  • Authors:

  • Victoria Wang;Dejan Marković

  • Affiliations:

  • University of California, Los Angeles;University of California, Los Angeles

  • Venue:
  • Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
  • Year:
  • 2008

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Abstract

This paper describes an alternate method to Monte Carlo for calculating circuit node voltage and branch current variances due to random process variability. Recent results show that the complex models traditionally used to describe random process variations of a transistor can be replaced by a single independent current noise source with a variance dependent on the transistor's size and operating points. As a result, each transistor affected by random process variability can be modeled as a deterministic device in parallel with a current noise source. By replacing all the transistors in a circuit with this model, the spatial voltage variances of circuit nodes can be calculated through linear small-signal analysis. The idea is presented in this paper and a tool implemented for Berkeley SPICE is described. The results of the variability SPICE tool match the results from Monte Carlo run in SPECTRE, with an accuracy determined by the accuracy of the random process variability model. For example, the standard deviations computed by the tool are within a 5.0% accuracy of those calculated through measured silicon data which has a fitting error of 5.4%. The Monte Carlo method computes node variances in a time proportional to the number of circuit nodes and the number of iterations, whereas the computation time required by the variability tool is only a function of the number of circuit nodes. For large analog designs this results in a significant speed-up in the amount of time required to calculate circuit node variances.