Variability in sub-100nm SRAM designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Overview of candidate device technologies for storage-class memory
IBM Journal of Research and Development
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane
IEEE Design & Test
Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
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Novel nonvolatile memory (NVM) technologies are gaining significant attention from semiconductor industry in the competition of universal memory development. However, as nanoscale devices, these emerging NVMs suffer from the intrinsic technology challenges such as large process variations. The importance of effective statistical approaches for yield estimation and robust design arises in the commercialization of the emerging nonvolatile memory technologies. In this paper, we used Spin-Transfer Torque Random Access Memory (STT-RAM) as an example to explain some new memory failures mechanisms we have to face in the emerging memory technologies. Then, we applied a mixture importance sampling methodology to enable yield-driven design and extended its application beyond memories to peripheral circuits and logic blocks. The goal of these discussions is to propose a universal statistical methodology to predict memory loss and enable robust design practices.