A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies

Authors:
Rajiv Joshi;Rouwaida Kanj;Keunwoo Kim;Richard Williams;Ching-Te Chuang
Affiliations:
IBM;IBM;IBM;IBM;IBM
Venue:
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Year:
2007

Citing 3
Cited 2

Operation and modeling of the MOS transistor

Operation and modeling of the MOS transistor
Review and future prospects of low-voltage RAM circuits

IBM Journal of Research and Development
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events

Proceedings of the 43rd annual Design Automation Conference

A novel column-decoupled 8T cell for low-power differential and domino-based SRAM design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a novel dynamic supply boosting technique for low voltage SRAMs at/beyond 65 nm PD/SOI technologies. For the first time the technique exploits the capacitive coupling effect in a floating-body PD/SOI device to dynamically boost the virtual array supply voltage during Read operation, thus improving the Read performance, Read/half-select stability, and Vmin. This enables significant reduction of the standby cell power and circuit active power in a single supply methodology. The performance and parametric yield improvements in the presence of variability are analyzed/validated using precise and fast Monte Carlo statistical circuit simulations with mixture importance sampling. Fabricated column-based 65nm PD/SOI SRAM circuits are confirmed with simulations and physical analysis and are shown to operate at 0.4 V. to 0.5V.