SRAM write-ability improvement with transient negative bit-line voltage

Authors:
Saibal Mukhopadhyay;Rahul M. Rao;Jae-Joon Kim;Ching-Te Chuang
Affiliations:
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;IBM T. J. Watson Research Center, Yorktown Heights, NY;IBM T. J. Watson Research Center, Yorktown Heights, NY;National Chiao Tung University, Hscinchu, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2011

Citing 3
Cited 4

Digital systems engineering

Digital systems engineering
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events

Proceedings of the 43rd annual Design Automation Conference
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Single-ended, robust 8T SRAM cell for low-voltage operation

Microelectronics Journal
Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 103X reduction in the Write-failure probability with the proposed method.