Diagnosis and repair method of SoC memory

Authors:
Vladimir Hahanov;Anna Hahanova;Svetlana Chumachenko;Sergey Galagan
Affiliations:
Computer Engineering Faculty, Kharkov National University of Radioelectronics, Kharkov, Ukraine;Computer Engineering Faculty, Kharkov National University of Radioelectronics, Kharkov, Ukraine;Computer Engineering Faculty, Kharkov National University of Radioelectronics, Kharkov, Ukraine;Computer Engineering Faculty, Kharkov National University of Radioelectronics, Kharkov, Ukraine
Venue:
WSEAS Transactions on Circuits and Systems
Year:
2008

Citing 8
Cited 1

System-on-a-chip verification: methodology and techniques

System-on-a-chip verification: methodology and techniques
Mapping and Repairing Embedded-Memory Defects

IEEE Design & Test
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield

IEEE Design & Test
Writing Testbenches: Functional Verification of HDL Models, Second Edition

Writing Testbenches: Functional Verification of HDL Models, Second Edition
Guest Editors' Introduction: Design for Yield and Reliability

IEEE Design & Test
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure

IEEE Design & Test
The State-of-Art and Future Trends in Testing Embedded Memories

MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
A Platform-Based Taxonomy for ESL Design

IEEE Design & Test

Datapath error detection with no detection latency for high-performance microprocessors

WSEAS Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

An exact method of memory elements diagnosis and repair by spares that enables to cover a set of fault cells by minimally possible quantity of spares is represented. The method is oriented on implementation to the Infrastructure Intellectual Property for SoC functionality. It enables to raise yield essentially on the electronic technology market by means of faulty chip repair in the process of production and operation, as well as to increase the life cycle duration of memory matrixes by repair of them in real time.