A Strategy for Mixed-Signal Yield Improvement
IEEE Design & Test
Embedded Timing Analysis: A SoC Infrastructure
IEEE Design & Test
IEEE Design & Test
Embedded Robustness IPs for Transient-Error-Free ICs
IEEE Design & Test
Using embedded infrastructure IP for SOC post-silicon verification
Proceedings of the 40th annual Design Automation Conference
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Impact of Design-Manufacturing Interface on SoC Design Methodologies
IEEE Design & Test
FAME: A Fault-Pattern Based Memory Failure Analysis Framework
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Challenges in Embedded Memory Design and Test
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
File System Interfaces for Embedded Software Development
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
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In addition to the functional IP cores, today's SOC necessitates embedding a special family of IP blocks, called Infrastructure IP blocks. These are meant to ensure the manufacturability of the SOC and to achieve adequate levels of yield and reliability. The Infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This paper analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of such Infrastructure IP. It also describes several examples of such embedded IPs for detection, analysis and correction.