Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
IEEE Spectrum
Bridging the Gap Between Embedded Test and ATE
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Embedding infrastructure IP for SOC yield improvement
Proceedings of the 39th annual Design Automation Conference
Using embedded infrastructure IP for SOC post-silicon verification
Proceedings of the 40th annual Design Automation Conference
Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An integrated BIST-based flow streamlines debugging and fault diagnosis of increasingly complex SoC devices. This methodology can help meet the requirement for shorter time to market.