Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Infrastructure IP for Configuration and Test of Boards and Systems
IEEE Design & Test
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip
Proceedings of the 44th annual Design Automation Conference
Robust concurrent online testing of network-on-chip-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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