Guest Editor's Introduction: What is Infrastructure IP?
IEEE Design & Test
Lee Distance and Topological Properties of k-ary n-cubes
IEEE Transactions on Computers
Peak Power Control for a QoS Capable On-Chip Network
ICPP '05 Proceedings of the 2005 International Conference on Parallel Processing
Integrating BIST Techniques for On-Line SoC Testing
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Dense Gaussian networks: suitable topologies for on-chip multiprocessors
International Journal of Parallel Programming
An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
FreePDK: An Open-Source Variation-Aware Design Kit
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip
Proceedings of the 44th annual Design Automation Conference
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
SIAM Journal on Discrete Mathematics
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Concurrent on-line testing (COLT) of manycore systems-on-chip (SoC) has been recently proposed by researchers in response to the growing threat of electronic wear-out to system operational lifetimes and to the increasing reliability and availability demands of safety-critical applications. Previous research in concurrent on-line testing has focused on centralized approaches to manage core testing while the system is available to execute normal user applications. However, as technology scaling allows dozens and hundreds of processing cores to be placed on a single chip, these centralized approaches are not scalable solutions. In this paper, a distributed concurrent on-line test scheduling protocol is proposed and evaluated against previously developed solutions. Our experiments show that a distributed COLT scheduler can test a moderately-sized SoC with a speedup of 3.85 over centralized approaches while consuming 84% less energy, and performance benefits improve as the number of cores per chip increases. This research also presents a core test ordering algorithm - Code-Division Core Test Scheduling - that provides an additional 40% reduction in system test latency compared to other schedulers.