Dense Gaussian networks: suitable topologies for on-chip multiprocessors

Authors:
Carmen Martínez;Enrique Vallejo;Ramón Beivide;Cruz Izu;Miquel Moretó
Affiliations:
Group of Computer Architecture, University of Cantabria, Santander, Spain;Group of Computer Architecture, University of Cantabria, Santander, Spain;Group of Computer Architecture, University of Cantabria, Santander, Spain;Department of Computer Science, The University of Adelaide, Adelaide, Australia;Computer Architecture Department, Technical University of Catalonia (UPC), Barcelona, Spain
Venue:
International Journal of Parallel Programming
Year:
2006

Citing 17
Cited 2

Optimized mesh-connected networks for SIMD and MIMD architectures

ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Discrete Optimization Problem in Local Networks and Data Alignment

IEEE Transactions on Computers
An optimization problem in distributed loop computer networks

Proceedings of the third international conference on Combinatorial mathematics
Algorithms for scalable synchronization on shared-memory multiprocessors

ACM Transactions on Computer Systems (TOCS)
Optimal Distance Networks of Low Degree for Parallel Computers

IEEE Transactions on Computers
A Combinatorial Problem Related to Multimodule Memory Organizations

Journal of the ACM (JACM)
Improving parallel system performance by changing the arrangement of the network links

Proceedings of the 14th international conference on Supercomputing
Piranha: a scalable architecture based on single-chip multiprocessing

Proceedings of the 27th annual international symposium on Computer architecture
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers

IEEE Transactions on Parallel and Distributed Systems
Efficient All-to-All Broadcast in All-Port Mesh and Torus Networks

HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Token coherence: decoupling performance and correctness

Proceedings of the 30th annual international symposium on Computer architecture
Performance analysis of the Alpha 21364-based HP GS1280 multiprocessor

Proceedings of the 30th annual international symposium on Computer architecture
Low-Latency Virtual-Channel Routers for On-Chip Networks

Proceedings of the 31st annual international symposium on Computer architecture
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism

Proceedings of the 31st annual international symposium on Computer architecture
Improving Multiple-CMP Systems Using Token Coherence

HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Practicable Layouts for Optimal Circulant Graphs

PDP '05 Proceedings of the 13th Euromicro Conference on Parallel, Distributed and Network-Based Processing
POWER4 system microarchitecture

IBM Journal of Research and Development

A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Dense bipartite circulants and their routing via rectangular twisted torus

Discrete Applied Mathematics

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper explores the suitability of dense circulant graphs of degree four for the design of on-chip interconnection networks. Networks based on these graphs reduce the Torus diameter in a factor √2, which translates into significant performance gains for unicast traffic. In addition, they are clearly superior to Tori when managing collective communications. This paper introduces a new two-dimensional node's labeling of the networks explored which simplifies their analysis and exploitation. In particular, it provides simple and optimal solutions to two important architectural issues: routing and broadcasting. Other implementation issues such as network folding and scalability by using hierarchical networks are also explored in this work.